AMD hiring 2023 Batch For Silicon Design Engineer

JOB	DETAILS
Company	AMD
Role	Silicon Design Engineer
Batch	2023
Education	BE / B.Tech / ME / M.Tech
Salary	14 LPA
Last Date	Apply Asap
Location	India
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JOB DESCRIPTION:

Responsibilities:
- Plan verification of complex digital design blocks by fully understanding the architecture and design specification.
- Testbench development in System Verilog and UVM to complete verification of RTL design in an efficient manner.
- Create and enhance constrained-random and/or directed verification scenarios.
Debug tests with design engineers to deliver functionally correct design block.
- Responsible for verification quality metrics like pass rates, code coverage and functional coverage.

General requirements:
- Good exposure to UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs.
Understanding of state of the art of verification techniques, including assertion and coverage-driven verification.
Strong understanding of different phases of ASIC and/or full custom chip development is required.
Knowledge of standard protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus
Knowledge of verification flows such as gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.
Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.

Special Requirements:
Implementing verification environment using advanced verification methodology such as UVM or SystemVerilog.
Test plan development and test writing.
Analyzing and debugging failures using simulation tools such as Synopsys VCS or DVE to verify hard IPs, FPGA fabric or System-on-Chip.
Functional coverage writing, coverage collection and analysis, coverage closure.
Writing System Verilog assertions and assertion based verification; and.
Running regressions, automation using scripting languages such as PERL and verification closure.

Education Requirements:

Bachelors or Masters degree in computer engineering/Electrical Engineering