AMD hiring 2023 Batch For Silicon Design Engineer
| JOB | DETAILS |
|---|---|
| Company | AMD |
| Role | Silicon Design Engineer |
| Batch | 2023 |
| Education | BE / B.Tech / ME / M.Tech |
| Salary | 14 LPA |
| Last Date | Apply Asap |
| Location | India |
| More 2022 Batch Job Updates | CLICK HERE |
| More 2023 Batch Job Updates | CLICK HERE |
| More 2024 Batch Job Updates | CLICK HERE |
| For Daily Job Updates | CLICK HERE |
Companies Hiring Now:
1. Copeland Offcampus Drive For 2023 Batch - Apply Now
2. Solvative Internship Drive for 2022, 2023, 2024 Batches - Apply Now
3. Consilio hiring 2023, 2022, 2021 Batches For Associate - Data Operations - Apply Now
4. Wissen Offcampus hiring 2022, 2023 Batches | Wissen Offcampus Drive 2023 - Apply Now
5. MAQ Software Hiring 2023, 2022, 2021 Batches For SWE | MAQ Software Hiring New Graduates for Software Engineer role - Apply Now
6. Salesforce Referral For 2025 Batch For SWE Intern | Salesforce Internship Drive for 2025 Batch - Apply Now
7. Walmart hiring 2024 Batch For Graduate Intern | Walmart Internship Drive 2023 - Apply Now
8. Hashicorp hiring 2024, 2025, 2026 Batches For SWE Intern - Apply Now
9. TCS Offcampus Drive for 2023, 2024 Batches | TCS Offcampus Drive 2023 - Apply Now
10. Coinbase hiring 2023, 2024, 2025 Batches For SWE Intern - Apply Now
JOB DESCRIPTION:
Responsibilities: - Plan verification of complex digital design blocks by fully understanding the architecture and design specification. - Testbench development in System Verilog and UVM to complete verification of RTL design in an efficient manner. - Create and enhance constrained-random and/or directed verification scenarios. Debug tests with design engineers to deliver functionally correct design block. - Responsible for verification quality metrics like pass rates, code coverage and functional coverage. General requirements: - Good exposure to UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs. Understanding of state of the art of verification techniques, including assertion and coverage-driven verification. Strong understanding of different phases of ASIC and/or full custom chip development is required. Knowledge of standard protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus Knowledge of verification flows such as gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus. Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus. Special Requirements: Implementing verification environment using advanced verification methodology such as UVM or SystemVerilog. Test plan development and test writing. Analyzing and debugging failures using simulation tools such as Synopsys VCS or DVE to verify hard IPs, FPGA fabric or System-on-Chip. Functional coverage writing, coverage collection and analysis, coverage closure. Writing System Verilog assertions and assertion based verification; and. Running regressions, automation using scripting languages such as PERL and verification closure. Education Requirements: Bachelors or Masters degree in computer engineering/Electrical Engineering
